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III-V/Si Multi-junction Solar Cells

Working closely with collaborators at the Ohio State University in the United States, we are developing high performance silicon bottom cells that are compatible with the integration of high efficiency III-V solar cells with silicon cells through adaptation of designs developed at UNSW and through novel processes and designs.

The combination of III-V materials with silicon offers the prospect of high efficiency with lower cost substrates than those in current use. The key breakthrough has been the integration of III-V materials with silicon to produce high quality material via deliberately offcut substrates (this is essentially like cutting a loaf of bread at an angle rather than flush). OSU have pioneered the use of a migration enhanced epitaxy (MEE) approach to grow Gallium Phosphide on silicon substrates, with outstanding material quality. We are working with OSU to develop the silicon bottom cell for these devices. Already this collaboration has yielded a record efficiency device with more to come in the very near future.

We are working on adapting the high efficiency silicon solar cell designs developed at UNSW over many years to be compatible with the processes that take place to allow integration of III-V materials with silicon. The typical structure we are using is shown below on the left, showing the nucleation layer for GaP/Si integration, a tunneling junction and the top GaAsP solar cell. Some interesting challenges have arisen with one example being some rather unwelcome effects on the minority carrier lifetimes in silicon (this determine how well your solar cell can ultimately perform). Utilising SPREEs great knowledge of silicon and expertise in processing of silicon these issues have been overcome. With support through the US Department of Energy Sunshot initiative we are working with industry partners to develop high efficiency III-V on silicon solar cells with the potential for commercial development. Analysis of the losses in the bottom silicon solar cell gives clues as to where gains can be found, the results of such analysis is shown below, right. This has allowed us to adjust our design in terms of emitter doping and the rear surface structure.

 

There is also work being done to look at making the silicon much thinner than the current thicknesses of 300-350 microns, to drive down material usage even further. This requires more novel silicon device designs, ranging from different materials to passivate the rear surface, to new ways of contacting the silicon with metal for power extraction. With generous financial support from ARENA we are working with collaborators we are looking at approaches, such as HIT (Heterojunction with Intrinsic Thin layer) structures, poly-Si based rear structures. We are looking at adapting a patented room temperature contacting method for the rear of the silicon sub-cell (see the silicon solar cell section for more details), as well as transition metal oxides for use as carrier selective contacts (CSCs) on the rear of the silicon bottom cell. For more information on these approaches see the page on Silicon Solar Cells.

Some of Our Recent Results

23.4% Monolithic Epitaxial GaAsP/Si Tandem Solar Cells and Quantification of the Role of Threading Dislocations

D. L. Lepkowski, T. J. Grassman, J. T. Boyer, D. J. Chmielewski, C. Yi, M. K. Juhl, A. H. Soeriyadi, N. Western, H. Mehrvarz, U. Römer, A. Ho-Baillie, C. Kerestes, D. Derkacs, S. G. Whipple, A. P. Stavrides, S. P. Bremner, S. A. Ringel 

Submitted to Solar Energy Materials and Solar Cells.

IIIVSiMJcrosssection.tiff
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